EDN

Is static timing analysis still valid?

SAN MATEO, Calif. — Static timing analysis is one of the pilings upon which the whole edifice of modern IC design has been erected. But this vital technique itself rests upon assumptions that may no ...
EDN

Practical Applications of Statistical Static Timing Analysis

As the electronic design industry continues to push the limits of Moore's Law, a paradigm shift in timing analysis must be considered. The major reason for this is overly pessimistic timing analysis, ...
Electronic Design

EDA Vendors Should Improve The Runtime Performance Of Path-Based Analysis

This file type includes high resolution graphics and schematics. The first time I signed off a design for fabrication, I was a physical design lead working for an ASIC vendor. My company had a very ...
Electronic Design

Oh, The Pain (Of Timing Closure At 28 nm)

What to do, what to do? Chip complexity continues to grow and design schedules are more aggressive, yet design teams are staying the same size or even being scaled back. Something has to give. A key ...