IEEE

Implementation of the compression function for selected SHA-3 candidates on FPGA

Abstract: Implementation of the main building block (compression function) for five different SHA-3 candidates on reconfigurable hardware is presented. The five candidates, namely Blue Midnight Wish, ...
IEEE

Implementation of 256-Bit AES and SHA3 on FPGA

Abstract: The work discusses an implementation of the SHA3 algorithm and AES encryption/decryption algorithms which is of 256 bits using Verilog HDL on FPGA. The approach emphasizes optimizing ...